Leak: Zen 6 CCDs to Come in 12 and 32 Cores — Up to 3MB L128 Cache
Well-known insider @9550pro (HXL) published a brief, but important information about future CCD blocks of the architecture Zen 6 from AMD. According to his message, the company is preparing two types of chiplets: 12-core with 48MB L3 cache и 32-core with 128MB L3 cacheWhen asked by one of the subscribers whether this information applies to Zen 6, HXL briefly responded: "Yes" — confirming that we are talking about the next generation of AMD CPUs.
Appearance 32-core CCD with 128 MB cache — this is a radical change in architecture scaling, especially considering that the current Zen 5/5C chiplets are limited to 8 or 16 cores per CCD. This could indicate a significant design overhaul towards tighter integration of cores and increased cache memory, probably in Zen 6C variants for server solutions.
Secondary block — 12 cores with 48 MB L3 — rather, it is a basic CCD for client processors on Zen 6. The cache proportion (4 MB per core) corresponds to AMD standards of the latest generations. Such chiplets will probably become the basis for new Ryzen and EPYC series in the consumer and enterprise segments.
These parameters are consistent with earlier leaks about the platform. EPYC Venice, where chiplets with 12 cores and configurations of up to 256 cores in a single CPU were indicated. Zen 6 is expected to be AMD's first generation to be built on TSMC's 2nm process., which makes it possible to expand on such a large scale.
AMD has not officially commented on these figures yet, but @9550pro sources are traditionally close to suppliers and have a good reputation. If the leak is confirmed, Zen 6 Will Be AMD's Most Scalable CPU Generation Ever, and will bring with it a qualitative leap in computing capabilities in both the server and consumer segments.
