AMD EPYC Venice: Up to 256 Cores and 512 Threads in Zen 6 Server CPUs
New data has leaked online AMD EPYC 9006 Venice Server Processor Series, which will be the company's first chips released TSMC 2nm process technologyWith the upcoming 2025 launch, details about the configuration, architecture, and power consumption of the new products have begun to emerge. Leaks have come from Asian forums including Baidu, as well as sources close to AMD's server OEM partners.
According to this data, the line will be divided into Zen 6 and Zen 6C modifications, as was previously the case with Zen 4/5 and Zen 4C/5C. Standard Zen 6 chips will receive up to 96 cores and 192 threads, while the compact Zen 6C models promise up to 256 cores and 512 threads — twice the maximum of current Turin processors. The architecture assumes the use of up to 8 CCD blocks on the chip, each of which contains 12 cores.
Special attention deserves L3 cache size: Each CCD is reported to contain up to 128 MB of L3, equivalent to 2 MB cache per core in Zen 6C variants. The central IOD will be expanded to increase I/O capabilities, including support for 12- and 16-channel DDR5 memory. Boards with SP7 and SP8 sockets will divide the line into levels: SP7 - for high-performance HPC scenarios, SP8 - for more energy-efficient solutions.
Of interest are also TDP metrics for future EPYC chips: According to source Bionic_Squash, Zen 6C on SP7 can reach 600 W, while the SP8 versions will remain in the 350-400W range. This is a sharp increase compared to the Zen 5 series, but it is justified by the density of the compute units.
