Synopsys Advances Record-Bandwidth LPDDR6 on TSMC N2P Process

Synopsys announced the successful bring-up-verification of the LPDDR6 IP block, created using TSMC N2P process technologyThis milestone signifies that the IP integration has completed its first run on silicon and is ready for further licensing by partners. According to Synopsys, the controller and PHY interface of the new solution are already showing throughput up to 86 GB/s, which corresponds to the current level JEDEC standard.

Thanks to N2P features including advanced metal stacks and I/O libraries, we were able to reduce power consumption and chip area. This makes the new IP particularly relevant for embedded AI platforms and energy-efficient solutions, including smartphones and laptops. The device includes a controller that supports all JEDEC functions, including timing control and power-saving state transitions.

It is particularly emphasized that the N2P process provides the best on the market PPA indicators (performance, power, area), which allows for the high logic density required for LPDDR6. The standard specification itself provides up to 14,4 GB/s per pin, which could potentially deliver throughput above 115 GB/s with optimal implementation.

LPDDR6 is expected to enter the mainstream market in 2026, and Synopsys expects its IP to become a key component in mobile and AI-focused SoCs. This new product demonstrates how advanced lithography technologies can accelerate the adoption of new memory standards in commercial devices.